1. Field of the Invention
The present invention relates to an XY address solid-state image pickup apparatus having a pixel array made up a plurality of pixels two-dimensionally arranged and, more particularly, to an XY address solid-state image pickup apparatus having a scanning circuit that may perform a thinned-out scanning with one out of every arbitrary number of stages or an arbitrary number of stages as a unit.
2. Description of the Related Art
In known XY address solid-state image pickup apparatuses having a pixel array made up a plurality of pixels two-dimensionally arranged, horizontal and vertical scanning circuits for sequentially selecting a pixel employ a shift register. Known as one type of such shift register is a clocked CMOS shift register that is constructed by cascading clocked inverters. FIG. 1 shows the construction of such a shift register. Shown in FIG. 1 are first clocked inverters 100-1 and second clocked inverters 100-2, and one first clocked inverter 100-I and one second clocked inverter 100-2 are cascaded to form a shift register unit 101. A number of shift register units 101 are again cascaded to form a shift register. Each shift register unit 101 inverts an input signal .phi. ST at the timings of the clock pulses .phi. 1 and .phi. 2, and multiple stages of such shift register units 101 function as a shift register
Referring to the timing diagram in FIG. 2, the operation of the shift register in FIG. 1 is now discussed. At time t.sub.ST, the input signal .phi. ST is driven and remains high level for a duration of one period of the clock .phi.1. When the clock .phi.2 is high level, the first clocked inverters 100-1 become active, and data at nodes SR 0.0, SR 1.0, SR 2.0, SR 3.0, SR 4.0, SR 5.0, SR 6.0, and SR 7.0 are inverted and then shifted to SR 0.5, SR 1.5, SR 2.5, SR 3.5, SR 4.5, SR 5.5, SR 6.5 and SR 7.5, respectively, When the clock .phi. 1 is high level, the second clocked inverters 100-2 become active, data at nodes R 0.5, SR 1,5, SR 2.5, SR 3.5, SR 4.5, SR 5.5, SR 6.5 and SR 7.5 are inverted and shifted to SR 100, SR 2.0, SR 3.0, SR 4.0, SR 5.0, SR 6.0, SR 7.0 and SR 8.0, respectively. At times t.sub.01, t.sub.02, t.sub.03, t.sub.04, t.sub.05, t.sub.06, t.sub.07, and t.sub.08, a high level thus appears at nodes SR 1.0, SR, 2.0, SR 3.0, SR 4.0, SR 5.0, SR 6.0, SR 7.0 and SR 8.0, respectively. This high level signal is used as a selection signal output by the scanning circuit in the solid-state image pickup apparatus, and the pixels are thus sequentially selected to read out pixel signals.
In the scanning circuit of the solid-state image pickup device constructed of such a shift register, after the input signal .phi. ST is input to the shift register at each scan cycle, a fast clock and standard clock are alternately input to drive the shift register, and a selection signal is output every predetermined number of stages to perform a thinned-out scanning by not using the output signal from a fast clock input section as a selection signal. In the thinned-out scanning, the selection signal is output every predetermined number of stages.
This operation is discussed referring to the timing diagram in FIG. 3. At time t.sub.ST, an input signal .phi. ST having a high level for a duration of one period of a clock .phi. 1 is input to node SR 0.0. The subsequent operation of the shift register is similar to that of FIG. 2. In this thinned-out scanning operation, however, the periods of the clocks .phi. 1 and .phi. 2 of t.sub.S1 to t.sub.S2, t.sub.S3 to t.sub.S4, t.sub.S5 to t.sub.S6, and t.sub.S7 to t.sub.S8 are set be shorter than those of t.sub.ST to t.sub.S1, t.sub.S2 to t.sub.S3, t.sub.S4 to t.sub.S5, and t.sub.6 to t.sub.7. The high level signals appearing at nodes SR 1.0, SR 3.0, SR 5.0, and SR 7.0 for durations of t.sub.S1 to t.sub.S2, t.sub.S3 to t.sub.S4, t.sub.S5 to t.sub.S6, and t.sub.S7 to t.sub.S8, respectively, are not used as the selection signals. The high level signals appearing at each of the nodes SR 2.0, SR 4.0, SR 6.0 and SR 8.0 are used as the selection signals output from the scanning circuit in the solid-state image pickup device, Thus, the thinned-out scanning is possible. In the thinned-out scanning described herein the scanning is performed every two pixels. By introducing a plurality of short periods into the clocks .phi. 1 and .phi. 2, the thinned-out signal that allows the apparatus to scan every predetermined number of pixels is obtained.
When the thinned-out scanning is achieved according to the method illustrated in the timing diagram in FIG. 3, the period of the driving clock of the shift register needs to be varied. Varying the period of the driving clock requires a complex control process. As the number of stages of the shift register increases, the load that the clock drives increases. An increased load along with an increased power consumption as a result of a high clock frequency gives rise to problems such as heat generation